1. Field of the Invention
The present invention relates to a bus system that permits data communication, across a system bus between a master core circuit and a slave core circuit, and relates in particular to a bus system wherein a master/slave core circuit is connected, through a master/slave I/F (Interface) circuit, to a system bus.
2. Related Arts
A data processing apparatus comprising a semiconductor integrated circuit, such as a so-called ASIC (Application Specific Integrated Circuit), is so designed that various types of master core circuits and various types of slave core circuits are connected to a single system bus.
The master core circuit is an integrated circuit such as a CPU, for example, that is mainly used to perform data processing, but that is also used, as needed, to perform data communication with the slave core circuit. The slave core circuit is an integrated circuit such as a RAM (Random Access Memory), for example, and subordinately participates in the data processing performed by the master core circuit.
However, the structure of a semiconductor integrated circuit has become complicated, and currently, a master/slave core circuit, including an IP (Intellectual Property) circuit that conforms to specific, established standards, may be combined with a different system bus. In this case, to prevent data communication problems, the design of the master/slave core circuit could be changed; however, in many cases, making such a change is difficult.
Therefore, a data processing apparatus has been devised wherein a master/slave core circuit is connected to a system bus via a master/slave I/F circuit, thereby avoiding the occurrence of associated problems when, through the system bus, data communication is performed by a master/slave core circuit conforming to different standards.
[Conventional Configuration]
The configuration of this conventional data processing apparatus will now be described while referring to FIGS. 7 to 9. As is shown in FIG. 7, a data processing apparatus 100 comprises a bus system 101, to which multiple types of master core circuits 102 and multiple types of slave core circuits 103 are connected.
The bus system 101 includes a system bus 105, multiple master I/F circuits 106, multiple slave I/F circuits 107, a master arbiter 108 and a slave arbiter 109, and the system bus 105 includes a WD (Write Data) bus 111 and an RD (Read Data) bus 112.
The WD bus 111 serves as a control bus and a data bus along which various commands and various data output by the master core circuits 102 are transmitted, through the master I/F circuits 106, to the slave I/F circuits 107. The RD bus 112 serves as a data bus along which various data output by the slave core circuits 103 are transmitted, through the slave I/F circuits 107, to the master I/F circuits 106.
The master core circuits 102 are respectively connected, through the master I/F circuits 106, to the system bus 105, and the slave core circuits 103 are respectively connected, through the slave I/F circuits 107, to the system bus 105.
The master arbiter 108 is connected to the master I/F circuits 106, and permits one of the master I/F circuits to occupy the system bus 105. The slave arbiter 109 is connected to the slave I/F circuits 107, and permits one of the slave I/F circuits 107 to occupy the system bus 105.
The WD bus 111 and the RD bus 112 are arranged in parallel. And along the WD bus 111, commands and communication data are transmitted from the master I/F circuits 106 to the slave I/F circuits 107, while along the RD bus 112, communication data from the slave I/F circuits 107 are transmitted to the master I/F circuits 106.
To simplify the explanation, hereinafter each paired master core circuit 102 and master I/F circuit 106 is called a master block 114, and each paired slave core circuit 103 and slave I/F circuit 107 is called a slave block 115.
[Conventional Operation]
The operation of the thus arranged data processing apparatus 100 will now be explained sequentially. In this case, master data denote various data that the master core circuits 102 store separately from commands and transmit to the slave core circuits 103 as needed. Slave data denote various data that the slave core circuits 103 store and transmit to the master core circuits 102 as needed.
For the transmission of master data from the master core circuit 102 to the slave core circuit 103, first, as is shown in FIG. 8, the master core circuit 102 transmits, to the master I/F circuit 106, a transmission command used to instruct the slave core circuit 103 to receive the master data.
When the master I/F circuit 106 occupies the WD bus 111, upon receiving the transmission command the master I/F circuit 106 transmits this command, through the system bus 105, to the slave I/F circuit 107. When, however, the master I/F circuit 106 does not occupy the WD bus 111, the master I/F circuit 106 transmits to the master arbiter 108 a request for permission to occupy the WD bus 111.
Upon receiving the occupation request, first, the master arbiter 108 receives an occupation end from another master block 114 currently occupying the WD bus 111 and permits the master block 114 that issued the occupation request to occupy the WD bus 111. Then, after the occupation of the bus has been effected, the master arbiter 108 transmits to the master I/F circuit 106 notification that the process has been completed, and the master I/F circuit 106 transmits a like notification to the master core circuit 102.
Since the master core circuit 102 again transmits a transmission command to the master I/F circuit 106, this command is transmitted from the master I/F circuit 106 through the system 105 to the slave I/F circuit 107, and is transmitted from the slave I/F circuit 107 to the slave core circuit 103. When, at this time, the slave core circuit 103 is performing another process and can not receive the master data, the slave core circuit 103 outputs a disable notification to the slave I/F circuit 107.
The disable notification is transmitted from the slave I/F circuit 107 through the system bus 105 to the master I/F circuit 106, and is transmitted from the master I/F circuit 106 to the master core circuit 102. In this case, the master core circuit 102 performs a so-called retry process to repeat the above operation a predetermined number of times, and issues a transmission error when the number of repetitions reaches a predetermined upper limit value.
When, before a transmission error is issued, the slave core circuit 103 is ready to handle the transmission command, the slave core circuit 103 outputs an enable notification to the slave I/F circuit 107. The enable notification from the salve I/F circuit 107 is then transmitted through the system bus 15 to the master I/F circuit 106, and is transmitted from the master I/F circuit 106 to the master core circuit 102.
Then, since the master core circuit 102 transmits master data to the master I/F circuit 106, the master data is transmitted from the master I/F circuit 106, through the occupied system bus 105, to the slave I/F circuit 107, and is transmitted from the slave I/F circuit 107 to the slave core circuit 103.
Further, when the master core circuit 102 obtains slave data from the slave core circuit 103, as is shown in FIG. 9, the master core circuit 102 transmits to the master I/F circuit 106 an acquisition command instructing the transmission of slave data by the slave core circuit 103.
The acquisition command is transmitted through the master I/F circuit 106, the system bus 105 and the salve I/F circuit 107 to the slave core circuit 103. When, at this time, the slave core circuit 103 is performing another process and can not transmit the master data, the retry process is performed as is described above. Then, when the slave core circuit 103 enables the transmission of master data, an enable notification is transmitted through the slave I/F circuit 107, the system bus 105 and the master I/F circuit 106 to the master core circuit 102.
At this time, the slave core circuit 103 prepares slave data, and after the slave data has been prepared, the slave core circuit 103 transmits to the slave I/F circuit 107 a request for permission to occupy the RD bus 112. Since the slave I/F circuit 107 transmits the occupation request to the slave arbiter 109, the slave arbiter 109 permits the slave block 115 that issued the occupation request to occupy the RD bus 112.
When notification that occupation of the RD bus 112 has been effected is transmitted by the slave arbiter 109 through the slave I/F circuit 107 to the slave core circuit 103, the slave data from the slave core circuit 103 is transmitted through the slave I/F circuit 107, the system bus 105 and the master I/F circuit 106 to the master core circuit 102.
Since in the data processing apparatus 100 the master core circuits 102 and the slave core circuits 103 are respectively connected to the system bus 105 through the master I/F circuits 106 and the slave I/F circuits 107, master core circuits 102 and slave core circuits 103 conforming to different standards can exchange data, through the system bus 105, without any problems being encountered.
However, as is shown in FIGS. 8 and 9, when the master core circuit 102 and the slave core circuit 103 perform data communication, all the data to be exchanged must be transmitted from the master or slave core circuit 102 or 103 to the other through the master/slave I/F circuit 106 or 107. Therefore, rapid data communication is difficult.